Question 1

Which of the following circuit parameters would be most likely to limit the maximum operating frequency of an IC flip- flop?

Accepted Answer

A)   Clock pulse HIGH and LOW time
B)   Propagation delay time
C)   Clock transition time
D)   Set- up and hold timeE) B) and C)
F) A) and B) B

Question 2

A_____accepts slow- changing input signals and generates clean, fast- transition output signals.

Accepted Answer

The answer of A_____accepts slow- changing input signals and generates...

Question 3

Which of the following flip- flop timing parameters indicates the time it takes a Q output to respond to an input?

Accepted Answer

A)   ts, th 
B)   tphl, tplh 
C)   tw(1) , tw(h) 
D)   fmaxE) A) and C)
F) All of the above

Question 4

A "D" flip- flop with a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?

Accepted Answer

A)   CLK = NGT, D - 0
B)   CLK = PGT, D = 1
C)   CLK = NGT, D = 1
D)   CLK = PGT, D = 0
E)   Both A and CF) A) and E)
G) B) and E)

Question 5

The new IEEE/ANSI symbols for latches and flip- flop use the letter "C" to denote:

Accepted Answer

A)   any input that will cause the device to change states.
B)   any input that controls when other inputs will have an effect on the output.
C)   the normal Q output.
D)   the SET and RESET inputs.E) A) and B)
F) A) and C)

Question 6

Generally, a flip- flop's hold- time is short enough to allow its output to be determined by the logic levels present at its synchronous control inputs just prior to the active clock transition.

Accepted Answer

A) True 
 B)False  True

Question 7

Which of the following best describes the characteristics of a MOD- 16 counter?

Accepted Answer

A)   Eight possible counts, a minimum count of 710, and frequency division by a factor of sixteen
B)   Sixteen possible counts, a maximum count of 1510, and frequency division by a factor of eight
C)   Eight possible counts, a maximum count of 710 and frequency division by a factor of eight
D)   Sixteen possible counts, a maximum count of 1510, and frequency division by a factor of sixteenE) C) and D)
F) A) and B)

Question 8

Which of the following logic devices is specifically designed to produce clean, fast- changing output signals?

Accepted Answer

A)   NAND latch
B)   NOR latch
C)   Schmitt- trigger
D)   J- K flip- flopE) C) and D)
F) A) and C)

Question 9

Which statement best describes the action of a NAND gate latch?

Accepted Answer

A)   The SET and CLEAR inputs are normally HIGH with one or the other input pulsed LOW to change the outputs.
B)   The SET input is normally LOW, the CLEAR input is normally HIGH, the SET input is pulsed HIGH to change the outputs.
C)   The SET and CLEAR inputs are normally LOW with one or the other pulsed LOW to change the outputs.
D)   The SET input is normally HIGH, the CLEAR input is normally LOW, the CLEAR input is pulsed LOW to change the outputs.E) B) and C)
F) All of the above

Question 10

74xxx standard logic chips are found in the megafunction library of the Quartus II development software.

Accepted Answer

A) True 
 B)False

Question 11

The difference between a D- latch and an edge- triggered D- type flip- flop is that the latch:

Accepted Answer

A)   is controlled by the logic level at its ENABLE input rather than a CLK transition.
B)   triggers on either the rising or falling edge of an ENABLE signal rather than the CLK input logic level.
C)   always "latches" the Q output to the D input regardless of other inputs.
D)   always "latches" the Q output to the complement of the D input regardless of other inputs.E) All of the above
F) A) and C) A

Question 12

A small triangle at the CLK input on a standard flip- flop symbol indicates that any change in the output is triggered by a clock transition.

Accepted Answer

A) True 
 B)False

Question 13

A primary difference between a D flip- flop and the J- K and S- C flip- flops is the fact that:

Accepted Answer

A)   a "D" flip- flop has one control input and no clock input.
B)   a "D" flip- flop has only one control input and two clock inputs.
C)   a "D" flip- flop has only one control input and one clock input.
D)   a "D" flip- flop has two control inputs and no clock input.E) All of the above
F) B) and C)

Question 14

What is the output frequency of a three- stage binary counter with an input clock frequency of 80 kHz?

Accepted Answer

A)   20 kHz
B)   10 kHz
C)   15 kHz
D)   5 kHzE) A) and D)
F) B) and D)

Question 15

The Q output of a flip- flop is normally HIGH when the device is in the "CLEAR" or "RESET" state.

Accepted Answer

A) True 
 B)False

Question 16

_____flip- flop inputs override all other inputs.

Accepted Answer

The answer of _____flip- flop inputs override all other inputs....

Question 17

A one- shot has a stable output state that is essentially interrupted by the trigger input. Once interrupted, the output goes to the opposite state for a specific amount of time.

Accepted Answer

A) True 
 B)False

Question 18

Forcing the SET input LOW on a NAND gate latch generates outputs of:

Accepted Answer

A)   Q = 1 and  = 1
B)   Q = 0 and  = 1
C)   Q = 0 and  = 0
D)   Q = 1 and  = 0E) C) and D)
F) A) and B)

Question 19

Which of the following best describes the normal logical operation of a NOR gate latch?

Accepted Answer

A)   Inactive SET and CLEAR inputs = 1, active SET input = 1, active CLEAR input = 0
B)   Inactive SET and CLEAR inputs = 0, active SET or CLEAR inputs = 1
C)   Inactive SET and CLEAR inputs = 0, active SET or CLEAR inputs = 0
D)   Inactive SET and CLEAR inputs = 1, active SET input = 0, active CLEAR input = 1E) All of the above
F) A) and C)

Question 20

Which of the following statements regarding the small triangles in the IEEE/ANSI symbols for flip- flops is TRUE?

Accepted Answer

A)   A triangle within the rectangle means edge- triggered and an external triangle indicates an active LOW input.
B)   Triangles internal and external to the rectangle indicate active LOW inputs are required.
C)   A triangle external to the rectangle means edge- triggered and internal triangles indicate active LOW inputs.
D)   Internal triangles require active LOW inputs whereas external triangles indicate "Don't Care" conditions.E) B) and D)
F) A) and B)

Exam 5: Flip-Flops and Related Devices

Which of the following circuit parameters would be most likely to limit the maximum operating frequency of an IC flip- flop?

Correct AnswerverifiedB

A_____accepts slow- changing input signals and generates clean, fast- transition output signals.

Correct AnswerverifiedShow Answer

Which of the following flip- flop timing parameters indicates the time it takes a Q output to respond to an input?

Correct AnswerverifiedShow Answer

A "D" flip- flop with a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?

Correct AnswerverifiedShow Answer

The new IEEE/ANSI symbols for latches and flip- flop use the letter "C" to denote:

Correct AnswerverifiedShow Answer

Generally, a flip- flop's hold- time is short enough to allow its output to be determined by the logic levels present at its synchronous control inputs just prior to the active clock transition.

Correct AnswerverifiedTrue

Which of the following best describes the characteristics of a MOD- 16 counter?

Correct AnswerverifiedShow Answer

Which of the following logic devices is specifically designed to produce clean, fast- changing output signals?

Correct AnswerverifiedShow Answer

Which statement best describes the action of a NAND gate latch?

Correct AnswerverifiedShow Answer

74xxx standard logic chips are found in the megafunction library of the Quartus II development software.

Correct AnswerverifiedShow Answer

The difference between a D- latch and an edge- triggered D- type flip- flop is that the latch:

Correct AnswerverifiedA

A small triangle at the CLK input on a standard flip- flop symbol indicates that any change in the output is triggered by a clock transition.

Correct AnswerverifiedShow Answer

A primary difference between a D flip- flop and the J- K and S- C flip- flops is the fact that:

Correct AnswerverifiedShow Answer

What is the output frequency of a three- stage binary counter with an input clock frequency of 80 kHz?

Correct AnswerverifiedShow Answer

The Q output of a flip- flop is normally HIGH when the device is in the "CLEAR" or "RESET" state.

Correct AnswerverifiedShow Answer

_____flip- flop inputs override all other inputs.

Correct AnswerverifiedShow Answer

A one- shot has a stable output state that is essentially interrupted by the trigger input. Once interrupted, the output goes to the opposite state for a specific amount of time.

Correct AnswerverifiedShow Answer

Forcing the SET input LOW on a NAND gate latch generates outputs of:

Correct AnswerverifiedShow Answer

Which of the following best describes the normal logical operation of a NOR gate latch?

Correct AnswerverifiedShow Answer

Which of the following statements regarding the small triangles in the IEEE/ANSI symbols for flip- flops is TRUE?

Correct AnswerverifiedShow Answer

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